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MP1906 80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 1 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. the future of analog ic technology description the MP1906 is a high-performance, 80v, gate driver that can drive two external n-mosfets in a half-bridge configuration with a 12v gate supply. it accepts independent gate input signals and provides shoot-through prevention. during under-voltage lockout, the output of the high- and low-side drivers goes low to prevent erratic operation under low supply conditions. the high-current driving capability and short dead time make it suitable for high-power and high- efficiency power applications, such as telecom dc-dc converters. the compact 8-pin soic package minimizes the component count and the board space. features ? drives two low-cost, high-efficiency n- mosfets ? 10v-16v gate drive supply ? 3.3v, 5v logic compatibility ? 80ns propagation delay ? less than 90 a quiescent current ? under-voltage lockout for both channels ? input-signal-overlap protection ? internal 150ns dead time ? available in a compact 8-pin soic package applications ? motor drivers ? half-bridge power supplies ? avionics dc-dc converters ? active-clamp forward converters all mps parts are lead-free and adhere to the rohs directive. for mps green status, please visit mps website under products, quality assurance page. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application vin=12v vcc sw bt hpwm lpwm gnd tg bg to output load up to 80v controller
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 2 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. ordering information part number* package top marking MP1906ds soic8 MP1906 *for tape & reel, add suffix ?z (e.g. MP1906ds?z). for rohs compliant packaging, add suffix ?lf (e.g. MP1906ds?lf?z) package reference vcc hpwm lpwm gnd bt tg sw bg 1 2 3 4 8 7 6 5 top view absolute maximum ratings (1) input voltage v cc .......................... -0.3v to +18v voltage on sw v sw ............................................. -0.3v (-5v < 10ns) to +100v voltage on bt v bt .............................. v sw +18v logic inputs ........................................................ -0.3 to (v cc +6.5v), or 18.5v for v cc 12v continuous power dissipation (t a = 25c) (2) ??????????????????...1.4w junction temperature .............. -40c to +150c lead temperature (solder 10sec) ............ 260c storage temperature ............... -55c to +150c recommended operating conditions (3) input voltage v cc .............................. 10v to 16v maximum voltage on sw v sw ..................... 80v logic inputs ......................................... 0v to v cc voltage slew rate on sw...................... < 50v/ns pwm frequency .................................. < 300khz operating junction temp. (t j ) . -40c to 125c thermal resistance (4) ja jc soic8 ..................................... 90 ...... 45 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb.
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 3 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical characteristics v cc = 12v, v sw =0v, no load on tg or bg, t a = 25c, unless otherwise noted. parameter symbol condition min typ max units supply current v cc quiescent current i ccq v lpwm =5v, v hpwm = 0v 70 90 110 a v cc operation current i cc f=50khz, c load bg =1nf 0.9 1.5 ma bootstrap quiescent current i btq v lpwm =5v, v hpwm = 0v 30 a bootstrap operation current i bt f=50khz, c load tg =1nf 0.7 1 ma sw bt leakage current i lk v sw =v bt =80v 0.1 0.5 a input lpwm falling threshold v lpwmf 0.8 v lpwm rising threshold v lpwmr 2.5 v hpwm falling threshold v hpwmf 0.8 v hpwm rising threshold v hpwmr 2.5 v under-voltage prot ection (uvlo) v cc rising threshold v ccthr 8.2 8.8 9.4 v v cc threshold hysteresis v ccthh 0.7 v bootstrap rising threshold v btthr 4.5 5.5 6.5 v bootstrap threshold hysteresis v btthh 0.65 v gate driver output low-side gate pull-up peak current (5) i bgu v bg =0v 350 ma low-side gate pull-down peak current (5) i bgd v bg =12v 1 a high-side gate pull-up peak current (5) i tgu v tg =0v 350 ma high-side gate pull-down peak current (5) i tgd v tg =12v 1 a propagation delays, dead times and output rising and falling times (c load =1nf cap) (please see timing diagram) turn-on propagation delay (tg) on tg v sw =0v 80 150 ns turn-off propagation delay (tg) off tg v sw =0v 80 150 ns turn-on rise time (tg) rise tg 50 100 ns turn-off fall time (tg) fall tg 30 100 ns turn-on propagation delay (bg) on bg 80 150 ns turn-off propagation delay (bg) off bg 80 150 ns turn-on rise time (bg) rise _ bg 50 100 ns turn-off fall time (bg) fall _ bg 30 100 ns deadtime, ls turn-off to hs turn- on & hs turn-on to ls turn-off dt 150 250 ns
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 4 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. electrical character istics(contiuued) v cc = 12v, v sw =0v, no load on tg or bg, t a = 25c, unless otherwise noted. parameter symbol condition min typ max units lpwm source current i lpwm i lpwm =5v -8 -3 -1 a hpwm sink current i hpwm i hpwm =5v 1 3 8 a floating gate driver bg-output-low to gnd v bgl i bg =100ma 0.4 0.7 v bg-output-high to rail v bgh i bg =-100ma, v bgh =v cc -v bg 1.5 1.7 v tg-output-low to sw v tgl i tg =100ma 0.4 0.7 v tg-output-high to rail v tgh i tg =-100ma, v tgh =v cc -v tg 1.5 1.7 v switching specifications minimum input pulse width to change the output (5) pwm_min 50 ns notes: 5) guaranteed by design lpwm t on t on t off t off t f t f t r t r bg hpwm tg figure 1: gate driver timing diagram
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 5 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical characteristics v dd =12v, v sw =0v, t a =+25c, unless otherwise noted. vccthh,vbtthh(v) vccthf,vbtthf(v) vtgl,vbgl(v) low level output voltage vs. temperature undervoltage lockout threshold vs. temperature (rising) undervoltage lockout hysteresis vs. temperature propagation delay vs. temperature undervoltage lockout threshold vs. temperature (falling) quiescent current vs. temperature vtgh,vbgh(v) high level output voltage vs. temperature 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2 -50 0 50 100 150 v tgh v bgh 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -50 0 50 100 150 v tgl v bgl 0 1 2 3 4 5 6 7 8 9 10 -50 0 50 100 150 vccth,vbtthr(v) v ccthr v btthr 0 1 2 3 4 5 6 7 8 9 10 -50 0 50 100 150 v btthf v ccthf 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -50 0 50 100 150 v btthh v ccthh -25 -5 15 35 55 75 95 115 135 155 -50 0 50 100 150 ton_tg,toff_tg,ton_bg, toff_bg(ns) t off_tg t off_bg t on_tg t on_bg 0 20 40 60 80 100 120 -50 0 50 100 150 i ccq i btq
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 6 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. typical performanc e characteristics v cc = 12v, v sw =0v, 1nf load on tg and bg, t a = 25c, unless otherwise noted. turn-on propagation delay turn-on propagation delay turn-off propagation delay turn-off propagation delay drive rise time(1nf load) drive rise time(1nf load) drive fall time(1nf load) drive fall time(1nf load) v hpwm 2v/div. v tg 5v/div. v hpwm 5v/div. v lpwm 5v/div. v tg 5v/div. v bg 10v/div. v tg 5v/div. v tg 5v/div. v hpwm 2v/div. v tg 5v/div. v lpwm 2v/div. v bg 5v/div. v bg 5v/div. v bg 5v/div. v lpwm 2v/div. v bg 5v/div. input signal overlap protection
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 7 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. pin functions pin # name description 1 vcc supply input. supplies power to all internal circuitry. requires a decoupling capacitor to ground placed close to this pin to ensure a stable and clean supply. 2 hpwm logic input for high-side gate driver output. 3 lpwm logic input for low-side gate driver output. active low. 4 gnd ground. 5 bg gate driver output for low-side mosfet. 6 sw source return for high-side mosfet. 7 tg gate driver output for high-side mosfet. 8 bt bootstrap. internal power supply pin for high-side floating driver. add a 1f ceramic bootstrap capacitor from bt to sw pin.
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 8 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. functional block diagram vcc hpwm lpwm bt tg sw bg gnd dead time control shoot through prevention vcc driver driver uvlo rdy turn-on delay level shift turn-on delay rdy uvlo figure 2: functional block diagram
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 9 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. operation switch shoot-through protection the input signals of hpwm and lpwm are independently controlled. input shoot-through protection circuitry prevents shoot-through between the tg and bg outputs. only one of the fet drivers can be on at one time. if hpwm is high and lpwm is low, both tg and bg are off. under voltage lockout when v cc or v bt goes below their respective uvlo threshold, both bg and tg outputs will go low to both fets. once v cc and v bt rises above the uvlo threshold, both tg and bg will stay low until there is a rising edge on either hpwm or lpwm. figure 3 shows the operation of the tg and bg under different hpwm and lpwm and uvlo conditions. hpwm tg bg lpwm figure 3: input/output timing diagram
MP1906?80v, half-bridge, gate driver MP1906 rev. 1.0 www.monolithicpower.com 10 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. application information reference design circuits half bridge motor driver in a half-bridge converter topology, the mosfet- driving signals have a dead time: hpwm and lpwm driven with alternating signals from the pwm controller. the input voltage can be up to 80v in this application. hpwm lpwm gnd tg sw bt vcc bg gnd vin=12v gnd a - + gnd gnd up to 80v hpwm lpwm MP1906 figure 4: half-bridge motor driver active-clamp-forward converter an active-clamp-forward-converter topology alternately drives the mosfets. the high-side mosfet and the capacitor, c reset , reset the power transformer in a lossless manner. this topology runs well at duty cycles exceeding 50%. however, the input voltage may not run at 80v. hpwm lpwm gnd tg sw bt vcc bg gnd vin=12v gnd gnd gnd up to 80v hpwm lpwm creset 1 3 2 4 secondary circuit MP1906 figure 5: active-clamp forward converter
MP1906? 80v half bridge gate driver notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP1906 rev. 1.0 www.monolithicpower.com 11 1/3/2013 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2013 mps. all rights reserved. package information soic8 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.004" inches max. 5) drawing conforms to jedec ms-012, variation aa. 6) drawing is not to scale. 0.010(0.25) bsc gauge plane

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